1. Field of the Invention
The present invention relates to a phase-locked loop (PLL) and more particularly relates to a PLL clock generator for generating clock pulses by reading a wobbling pattern on a given optical disc and to an optical disc drive including such a PLL clock generator.
2. Description of the Related Art
A recordable or rewritable optical disc such as a DVD-RAM, a DVD-R or a DVD-RW (which will be referred to herein as a “recordable optical disc” collectively) has spiral data recording tracks that wobble. A light beam that has been emitted toward, and reflected from, one of those recordable optical discs includes information representing modulation caused by the wobbling pattern on the optical disc (which will be referred to herein as “wobbling information”). A conventional optical disc drive generates a PLL multiplier clock signal in accordance with this wobbling information and uses that clock signal to perform a write operation synchronously with a clock pulse, to keep the linear velocity, at which the light beam scan the tracks, constant, or the like.
FIG. 7 is a block diagram showing a PLL clock generator 500 for use in a conventional optical disc drive. As shown in FIG. 7, when a wobble signal including wobbling information is input to the PLL clock generator 500, a binarizer 501 compares the level of the input signal with a predetermined zero level. If the level of the input signal is lower than that predetermined zero level, the binarizer 501 outputs “0”. On the other hand, if the level of the input signal is equal to or higher than the predetermined zero level, then the binarizer 501 outputs “1”. In this manner, a binary signal can be obtained.
A phase comparator 502 derives a phase difference between the binary signal and the output signal of a frequency divider 506 and outputs the difference as a phase error signal. More specifically, if the phase of the output signal of the frequency divider 506 is behind that of the binary signal, then the phase comparator 502 outputs an up signal of which the width represents the phase difference. On the other hand, if the phase of the output signal of the frequency divider 506 is ahead of that of the binary signal, then the phase comparator 502 outputs a down signal of which the width represents the phase difference. A charge pump 509 pumps current into a capacitor in a low pass filter 503 in response to the up signal and pumps out current from the capacitor in response to the down signal.
In response to the current that has been pumped out from, or pumped into, the capacitor by the charge pump 509, the low pass filter 503 performs a smoothing operation, thereby outputting a control voltage. Then, a VCO 504 outputs a clock signal of which the frequency is determined by the control voltage. On receiving the clock signal, the frequency divider 506 divides the frequency of the clock signal, thereby outputting a frequency-divided signal to the phase comparator 502. In this case, if the output signal of the frequency divider 506 has a phase lead, then the VCO 504 delays the phase of the clock signal by decreasing its oscillation frequency. On the other hand, if the output signal of the frequency divider 506 has a phase lag, then the VCO 504 advances the phase of the clock signal by increasing its oscillation frequency.
As a result of this operation, the PLL clock generator 500 generates a wobble clock signal, of which the frequency is n times as high as that of the input wobble signal (where n is determined by the frequency divider 506) and which is synchronized in phase with the binary signal. For example, if the input wobble signal has a frequency of 957 kHz and if the frequency divider 506 divides the frequency by 69 (i.e., when n=69), then the PLL clock generator 500 generates a wobble clock signal with a frequency of 66 MHz (=957 kHz×69). The optical disc drive will use this wobble clock signal as a write clock signal, a reference clock signal to generate various timing signals, and a reference clock signal to control a spindle motor.
In the PLL clock generator 500, the low pass filter 503 is designed so as to satisfy the response characteristic that the PLL clock generator 500 should exhibit. Generally speaking, to minimize the jitter of the wobble clock signal, the low pass filter 503 needs to have a lower cutoff frequency. However, if the cutoff frequency of the low pass filter 503 is decreased, then it will take a longer time for the PLL clock generator to accomplish phase locking or the capture range (i.e., a frequency range in which phase locking can be accomplished) may narrow. That is to say, some tradeoff is inevitable between the jitter minimization of the wobble clock signal and the time it takes to accomplish phase locking in the PLL clock generator or the phase-locking frequency range.
Thus, to overcome both of these problems at the same time, Japanese Laid-Open Publications Nos. 2001-126250 and 10-228730 disclose a technique of setting the loop gain of a PLL (which is normally represented by the amount of current pumped by the charge pump 509) relatively high during a phase locking operation and relatively low during a normal operation, respectively.
However, to switch the loop gain of the PLL in this manner, a circuit for changing the amounts of current to be pumped by the charge pump is needed, thus increasing the overall circuit scale unintentionally. Furthermore, if the response of the PLL is accelerated by increasing the loop gain thereof, then the PLL will have a decreased phase margin and easily lose its stability (e.g., phase locking state once accomplished collapses easily). For that reason, the gain cannot be increased excessively.